Instruction and Description of M68000

Instruction	Descritption
ABCD ADD AND ASL ASR	Add Decimal with Extend Add Logical AND Arithmetic Shift Left Arithmetic Shift Right
B<cc> BCHG BCLR BRA BSET BSR BTST	Branch Conditionally Bit Test and Change Bit Test and Clear Branch Always Bit Test and Set Branch to Subroutine Bit Test
CHK CLR CMP	Check Reigster Against Bounds Clear Operand Compare
DB<cc> DIVS DIVU	Decrement and Branch Conditionally Signed Divide Unsigned Divide
EOR EXG EXT	Exclusive OR Exchange Registers Sign Extend
JMP JSR	Jump Jump to Subroutine
LEA LINK LSL LSR	Load Effective Address Link Stack Logical Shift Left Logical Shift Right
MOVE MULS MULU	Move Source to Destination Signed Multiply Unsigned Multiply
NBCD NEG NOP NOT	Negate Decimal with Extened Negate No Operation One's Complement
OR	Logical OR
PEA	Push effective Address
RESET ROL ROR ROXL ROXR RTD RTE RTR RTS	Reset External Devices Rotate Left without Extend Rotate Right without Extend Rotate Left with Extend Rotate Right wiht Extend Return and Delocate Return from Exception Return and Restore Return from Subroutine
SBCD S<cc> STOP SUB SWAP	Subtract Decimal wiht Extend Set Conditional Stop Subtract Swap data register halves
TAS TRAP TRAPV TST	Test and Set Operand Trap Trap on Overflow Test

Bit Manipulation

Bit manipulation instructions manipulate a specific bit of a bit string (or operand treated as a bit string). Bit clear changes the specified bit to zero. Bit set changes the specified bit to one. Bit change modifies a specified bit, clearing a one bit to zero and setting a zero bit to one. In some processors, the value of the bit before modification is tested. Bit test examines the value of a specified bit.

Bit scan instructions search a bit string for the first bit that is set or cleared (depending on the processor).

• BTST Bit Test; Motorola 680x0, Motorola 68300; tests the value of a specified bit in a register or memory location (8 bit memory operands, 32 bit register operands); sets or clears flags
• BIT Bit Test; Intel 80x86; tests the value of a specified bit in a general register or memory location; sets or clears flags
• BCLR Bit Test and Clear; Motorola 680x0, Motorola 68300; tests the value of a specified bit in a register or memory location (8 bit memory operands, 32 bit register operands), then clears the specified bit to zero; sets or clears flags
• BTR Bit Test and Reset; Intel 80x86; tests the value of a specified bit in a general register or memory location, then clears (resets) the specified bit to one; sets or clears flags
• BSET Bit Test and Set; Motorola 680x0, Motorola 68300; tests the value of a specified bit in a register or memory location (8 bit memory operands, 32 bit register operands), then sets the specified bit to one; sets or clears flags
• BTS Bit Test and Set; Intel 80x86; tests the value of a specified bit in a general register or memory location, then sets the specified bit to one; sets or clears flags
• BCHG Bit Test and Change; Motorola 680x0, Motorola 68300; tests the value of a specified bit in a register or memory location (8 bit memory operands, 32 bit register operands), then either clears a one bit to zero or sets a zero bit to one; sets or clears flags
• BTC Bit Test and Complement; Intel 80x86; tests the value of a specified bit in a general register or memory location, then complements; sets or clears flags
• BSF Bit Scan Forward; Intel 80x86; scans a word (16 bits) or doubleword (32 bits) in memory or a general register from low-order to high-order (starting from bit index zero) for a one-bit and store the index of the first set bit into a register (if no set bit is found, the value of the destination register is undefined); sets or clears flags
• BSR Bit Scan Reverse; Intel 80x86; scans a word (16 bits) or doubleword (32 bits) in memory or a general register from high-order to low-order (starting from bit index 15 of a word or index 31 of a doubleword) for a one-bit and store the index of the first set bit into a register (if no set bit is found, the value of the destination register is undefined); sets or clears flags

For example bit manipulation search this :

https://en.wikipedia.org/wiki/Bit_manipulation#Example_of_bit_manipulation

Binary Coded Decimal

  Binary coded decimal (BCD) is a method for implementing lossless decimal arithmetic (including decimal fractions) on a binary computer. The most obvious uses involve money amounts where round-off error from using binary approximations is unacceptable. Some early computers used BCD exclusively.

    Decimal digits (0-9) can be encoded in a nibble (half a byte), with some left over bit patterns (hexadecimal A-F). In BCD operations, the processor performs ordinary binary computations, then adjusts the result to conform to BCD. For example, if you add the binary number 5 (bit pattern 0101) to binary number 6 (bit pattern 0110), you get the binary result of 11 (bit pattern 1011, or hexadecimal B). With BCD arithmetic, the processor would adjust the result to make it into a valid BCD result (which in this case would be bit pattern 0001 0001).

    BCD arithmetic includes BCD addition, BCD subtraction, BCD multiplication, BCD division, and BCD negate.

    The Intel 80x86 series uses a two step approach for BCD arithmetic. Instead of having separate BCD instructions, the normal binary addition and subtraction instructions are used, then hardware instructions are used to adjust the results to correct BCD results. There are instuctions for both packed and unpacked adjustments. The advantage of this approach is greater flexibility (more addressing modes and choices of arithmetic operations because of the use of regular binary integer instructions in the first step). The disadvantage of this approach is that it is slower and takes more memory.

    Pack (Motorola 680x0) converts byte encoded numeric data (such as ASCII or EBCDIC characters) into binary coded decimals. Unpack (Motorola 680x0) converts binary coded decimals into byte encoded numeric data (such as ASCII or EBCDIC characters). The ASCII adjustment field is $3030; the EBCDIC adjustment field is $F0F0.

• ABCD Add Decimal with Extend; Motorola 680x0, Motorola 68300; performs binary coded decimal addition of source plus destination plus extend bit, source and destination can be two data registers or two locations in memory with the two address pointer registers being predecremented; sets or clears flags
• SBCD Subtract Decimal with Extend; Motorola 680x0; performs binary coded decimal subtraction of source and extend bit from destination, source and destination can be two data registers or two locations in memory with the two address pointer registers being predecremented; sets or clears flags
• NBCD Negate Decimal with Extend; Motorola 680x0, Motorola 68300; performs tens complement of contents of a data register or memory location by performing decimal coded binary subtraction of destination and extend bit from zero; sets or clears flags
• DAA Decimal Adjust after Addition; Intel 80x86; adjusts the result of adding two valid packed decimal operands in AL register; sets or clears flags
• DAS Decimal Adjust after Subtraction; Intel 80x86; adjusts the result of subtracting two valid packed decimal operands in AL register; sets or clears flags
• AAA ASCII Adjust after Addition; Intel 80x86; changes the contents of register AL to a valid unpacked decimal number, and zeros the top 4 bits; sets or clears flags
• AAS ASCII Adjust after Subtraction; Intel 80x86; changes the contents of register AL to a valid unpacked decimal number, and zeros the top 4 bits; sets or clears flags
• AAM ASCII Adjust after Multiplication; Intel 80x86; corrects the result of a multiplication of two valid unpacked decimal numbers, the high order digit is left in AH, the low order digit in AL; sets or clears flags
• AAD ASCII Adjust before Division; Intel 80x86; modifies the numerator in AH and AL to prepare for the division of two valid unpacked decimal operands so that the quotient produced by the division will be a valid unpacked decimal number, AH should contain the high-order digit and AL the low-order digit, this instruction adjusts the value and places the result in AL, AH will contain zero.; sets or clears flags
• PACK Pack; Motorola 680x0; converts converts byte encoded numeric data (such as ASCII or EBCDIC characters) into binary coded decimals using an adjustment field ($3030 for ASCII, $F0F0 for EBCDIC), either from data register to data register or memory location to memory location with predecrement of address pointers; does not modify flags
• UNPK Unpack; Motorola 680x0; converts converts converts binary coded decimals into byte encoded numeric data (such as ASCII or EBCDIC characters) using an adjustment field ($3030 for ASCII, $F0F0 for EBCDIC), either from data register to data register or memory location to memory location with predecrement of address pointers; does not modify flags

Shift and Rotate

 Shift instructions move a bit string (or operand treated as a bit string) to the right or left, with excess bits discarded (although one or more bits might be preserved in flags). In arithmetic shift left or logical shift left zeros are shifted into the low-order bit. In arithmetic shift right the sign bit (most significant bit) is shifted into the high-order bit. In logical shift right zeros are shifted into the high-order bit.

Rotate instructions are similar to shift instructions, ecept that rotate instructions are circular, with the bits shifted out one end returning on the other end. Rotates can be to the left or right. Rotates can also employ an extend bit for multi-precision rotates.

Shift Operations

·         The ALU used in the 6800 performs shift and rotate operations.  The ASL, ASR and LSR instructions are shown in Figure 3.15

Figure 3.15: 6800 Shift Instruction :  (a) Arithmetic Shift Left (ASL)

(b) Arithmetic Shift Right (ASR)   (c) Logical Shift Right (LSR)

·         In the ASL operation, the MSB is shifted out of the data word into the Carry bit.  The LSB is filled with a 0.

·         The ASR operations shifts each bit to the right and moves the LSB into the  Carry bit.  The MSB, however, is retained and is also shifted into bit 6.  If the bits in the register are considered as a 2’s complement number; this method of shifting preserves the sign of the number.  The ASR is equivalent to dividing the number in the register by 2, regardless of the sign of the number.

·         The LSR operation simply shifts each bit one position to the right.  The MSB becomes a 0 and the LSB goes into the Carry bit.

                        Rotations

·         Two additional shifting instructions are ROL (Rotate Left) and ROR (Rotate Right) shown in Figure 3.16.  These are special forms of circular shifting, where the bits coming off one end of the word are inserted into the Carry bit, whereas the contents of the Carry bit are transferred into the vacated bit position.

·         There are many uses for Rotate instructions.  One application is to determine parity of a byte.  If the bits of the byte are successively shifted into the Carry bit, the number of 1’s can be counted and the parity can be determined as an ODD or EVEN number. 

6800 Data Manipulation Instructions

·  Addition is done by insert one number to the accumulator and then added it with another number by using ADD instruction.

·   Memory content are added with content of accumulator and result of addition will store into accumulator.

·   This instruction have three (3) addressing mode which is immediate, direct and extended.

·   Arithmetic operation will change value of flag N, Z, V, and C.  By checking C bit in CCR after addition, borrow value can be check.  If borrow value produce by before operation, so C flag will be set.

·   6800 is a 8-bit microprocessor, so it can handle only 255 maximum number.  The bigger number can be handle by using more than one byte memory.  Value of two byte can be store until 65,535 and three byte can be store until 16,777,215.

·   Number with multiple byte is store in side-by-side position.

·   In arithmetic multiple byte, the operation start at the lower byte and the carry value will be used in the operation on the upper byte.

·   The operation of ADC (Add to accumulator with carry) instruction are same as ADD instruction operation.  The differences are carry bit from lower byte operation are add to the current addition process (or upper byte).  This instruction have three (3) addressing mode which is immediate, direct and extended.

·   Subtraction operation have been done by using SUB (subtract from accumulator) and SBC (subtract from accumulator with carry).  SUB Instruction operation are not involve Carry flag.  SBC instruction will subtract 1 from result if C flag are set 1, if not their effect are same as SUB instruction operation.

·   The value in accumulator A can be added with value in accumulator B and their result store at accumulator A by using ABA (Add ACCB to ACCA) instruction also value in accumulator A can be subtract from accumulator B by using SBA (subtract ACCB from ACCA) instruction.

·   Another arithmetic instruction are NEG (Negate), CLR (Clear), INC (Increment) and DEC (Decrement).  NEG instruction are using for get the 2 complement’s operand.  CLR instruction are used to put zero value to the destination of the operand.  INC instruction are used to added 1 to the operand to get the address of the operation where else DEC instruction are used to subtract 1 from the operand. 

Integer Arithmetic

 The basic four integer arithmetic operations are addition, subtraction, multiplication, and division. Arithmetic operations can be signed or unsigned (unsigned is useful for effective address computations). Some older processors don’t include hardware multiplication and division. Some processors don’t include actual multiplication or division hardware, instead looking up the answer in a massive table of results embedded in the processor.

 A specialised, but common, form of addition is an increment instruction, which adds one to the contents of a register or memory location. For address computations, “increment” may mean the addition of a constant other than one. Some processors have “short” or “quick” addition instructions that extend increment to include a small range of positive values.

 A specialised, but common, form of subtraction is an decrement instruction, which subtracts one from the contents of a register or memory location. For address computations, “decrement” may mean the subtraction of a constant other than one. Some processors have “short” or “quick” subtraction instructions that extend decrement to include a small range of values.

 Compare instructions are used to examine one or more integers non-destructively. These are usually implemented by performing a subtraction in some shadow register or accumulator and then setting flags accordingly. Compare instructions can compare two integers, or can compare a single integer to zero. Triadic compare instructions compare a test value to an upper and lower limit, which can be useful for bounds and range checking.

Some processors have specific hardware support for large multi-byte integer arithmetic. Even if there is no specific support, generally carry and borrow flags can be used to implement software multi-byte arithmetic routines.

  Some processors have other special integer arithmetic operations. A clear instruction sets a register or memory location to zero. Some processors have special instructions for setting a register to a special value (such as pi) with additional guard bits also being set appropriately. A sign extend operation takes a small value and sign extends it to a larger storage format (such as byte to word). An arithmetic complement gives the arithmetic complement of a number (one’s complement). An arithmetic negate gives the arithmetic inverse of a number (subtract from zero; two’s complement).

Diagram

Address Movement

 Address movement instructions move addresses from one location to another. The source and destination locations are determined by the addressing modes, and can be registers or memory. Address movement instructions can come in a variety of sizes. Address movement instructions destroy the previous contents of the destination. Address movement instructions typically do not modify processor flags. When the destination is a register and the address is smaller than the full register size, the data might be placed only in the low order bits (leaving high order bits unchanged), or might be zero- or sign-extended to fill the entire register (some processors only use one choice, others permit the programmer to choose how this is handled).

• MOVEA.W Move Address (Word); Motorola 680x0, Motorola 68300; move an address word (16 bits) as sign-extended data (32 bits); memory to address register or register to address register; does not modify flags
• MOVEA.L Move Address (Longword); Motorola 680x0, Motorola 68300; move an address longword (32 bits); memory to address register or register to address register; does not modify flags
• LEA Load Effective Address; Motorola 680x0, Motorola 68300; computes an effective address and loads the result into an address register
• LA Load Address; RX format; IBM 360/370; computes an effective address and loads the 24-bit result (zero extended to 32-bits) into a general purpose register; does not affect condition code
• ENTA Enter A-register; MIX; move word or partial word field contents of index register to A-register (accumulator)
• ENTX Enter X-register; MIX; move word or partial word field contents of index register to X-register (extension)
• ENTi Enter I-register; MIX; move word or partial word field contents of index register to designated index register
• ENNA Enter Negative A-register; MIX; move word or partial word field contents of index register to A-register (accumulator), opposite sign loaded
• ENNX Enter Negative X-register; MIX; move word or partial word field contents of index register to X-register (extension), opposite sign loaded
• ENNi Enter Negative I-register; MIX; move word or partial word field contents of index register to designated index register, opposite sign loaded
• INCA Increase A-register; MIX; add word or partial word field contents of memory to A-register (accumulator), overflow toggle possibly set
• INCX Increase X-register; MIX; add word or partial word field contents of memory to X-register (extension), overflow toggle possibly set
• INCi Increase I-register; MIX; add word or partial word field contents of memory to designated index register, overflow toggle possibly set
• DECA Decrease A-register; MIX; subtract word or partial word field contents of memory from A-register (accumulator), overflow toggle possibly set
• DECX Decrease X-register; MIX; subtract word or partial word field contents of memory from X-register (extension), overflow toggle possibly set
• DECi Decrease I-register; MIX; subtract word or partial word field contents of memory from designated index register, overflow toggle possibly set
• PEA Push Effective Address; Motorola 680000; computes an effective address and pushes the result onto a stack (predecrementing an address register acting as a stack pointer)
• LINK Link Stack; Motorola 680000
• UNLK Unlink Stack; Motorola 680000

Data Movement

 Data movement instructions move data from one location to another. The source and destination locations are determined by the addressing modes, and can be registers or memory. Some processors have different instructions for loading registers and storing to memory, while other processors have a single instruction with flexible addressing modes. Data movement instructions generally have the greatest options for addressing modes. Data movement instructions typically come in a variety of sizes. Data movement instructions destroy the previous contents of the destination. Data movement instructions typically set and clear processor flags. When the destination is a register and the data is smaller than the full register size, the data might be placed only in the low order bits (leaving high order bits unchanged), or might be zero- or sign-extended to fill the entire register (some processors only use one choice, others permit the programmer to choose how this is handled). Register to register operations can usually have the same source and destination register.

    Earlier processors had different instructions and different names for different kinds of data movement, while most modern processors group data movement into a single symbolic name, with different kinds of data movement being indicated by address mode and size designation. A load instruction loads a register from memory. A store instruction stores the contents of a register into memory. A transfer instruction loads a register from another register. In processors that have separate names for different kinds of data moves, a memory to memory data move might be specially designated as a “move” instruction.

    An exchange instruction exchanges the contents of two registers, two memory locations, or a register and a memory location (although some processors only have register-register exchanges or other limitations).

    Some processors include versions of data movement instructions that can perform simple operations during the data move (such as compliment, negate, or absolute value).

    Some processors include instructions that can save (to memory) or restore (from memory) a block of registers at one time (useful for implementing subroutines).

    Some processors include instructions that can move a block of memory from one location to another at one time. If a processor includes string instructions, then there will usually be a string instruction that moves a string from one location in memory to another.

• MOVE Move Data; Motorola 680x0, Motorola 68300; move a byte (MOVE.B 8 bits), word (MOVE.W 16 bits), or longword (MOVE.L 32 bits) of data; memory to memory, memory to register, register to memory, or register to register; moves of byte and word data to registers leaves high order bits unchanged; sets or clears flags
• MOV Move Data; Intel 80x86; move a byte (8 bits), word (16 bits), or doubleword (32 bits) of data; memory to register, register to memory, or register to register (cannot move data from memory to memory or from segment register to segment register); does not affect flags
• MOV Move Data; DEC VAX; move a byte (MOVB 8 bits), word (MOVW 16 bits), longword (MOVL 32 bits), quadword (MOVQ 64 bits), octaword (MOVQ 128 bits), single precision floating (MOVF 32 bits), double precision floating (MOVD 64 bits), G floating (MOVG 64 bits), or H floating (MOVH 128 bits) of data; memory to memory, memory to register, register to memory, or register to register; moves of byte and word data to registers leaves high order bits unchanged; quadword, D float, and G float moves to or from registers are consecutive register pairs, octaword, and H float moves to or from registers are four consecutive registers; and sets or clears flags
• PUSH Push; Intel 80x86; decrement stack pointer and move a word (16 bits) or doubleword (32 bits) of data from memory or register (or byte of immediate data) onto stack; does not affect flags
• PUSHL Push Long; DEC VAX; decrement stack pointer (R14) and move a longword (32 bits) of data from memory or register onto stack; equivalent to MOVL src, -(SP), but shorter and executes faster; sets or clears flags
• POP Pop; Intel 80x86; move a word (16 bits) or doubleword (32 bits) of data from top of stack to register or memory and increment stack pointer; does not affect flags
• LR Load from Register; IBM 360/370; RR format; move a full word (32 bits) of data; register to register only; does not affect condition code
• L Load (from main storage); IBM 360/370; RX format; move a full word (32 bits) of data; main storage to register only; does not affect condition code
• LH Load Half-word; IBM 360/370; RX format; move a half-word (16 bits) of data; main storage to register only; does not affect condition code
• LDA Load A-register; MIX; move word or partial word field of data; main storage to accumulator only
• LDX Load X-register; MIX; move word or partial word field of data; main storage to extension register only
• LDi Load index-register; MIX; move word or partial word field of data; main storage to one of five index registers only
• ST Store (into main storage); IBM 360/370; RX format; move a full word (32 bits) of data; register to main storage only; does not affect condition code
• STH Store Half-word; IBM 360/370; RX format; move a half-word (16 bits) of data; register to main storage only; does not affect condition code
• STA Store A-register; MIX; move word or partial word field of data; accumulator to main storage only
• STX Store X-register; MIX; move word or partial word field of data; extension register to main storage only
• STi Store index-register; MIX; move word or partial word field of data; one of five index registers to main storage only
• MVI MoVe Immediate; IBM 360/370; SI format; move a character (8 bits) of data; immediate data to register only; does not affect condition code
• MOVEQ Move Quick; Motorola 680x0, Motorola 68300; moves byte (8 bits) of sign-extended data (32 bits) to a data register; sets or clears flags
• CLR Clear; Motorola 680x0, Motorola 68300; clears a register or contents of a memory location (.B 8, .W 16, or .L 32 bits) to zero; clears flags for memory and data registers, does not modify flags for address register
• CLR Clear; DEC VAX; clears a scalar quantity in register or memory to zero (CLRB 8 bits, CLRW 16 bits, CLRL 32 bits, CLRQ 64 bits, CLRO 128 bits, CLRF 32 bit float, or CLRD 64 bit float), an integer CLR will clear the same size floating point quantity because VAX floating point zero is represented as all zero bits; quadword and D float clears of registers are consecutive register pairs, octaword clears to registers are four consecutive registers; equivalent to MOVx #0, dst, but shorter and executes faster; sets or clears flags
• STZ Store Zero; MIX; move word or partial word field of data, store zero into designated word or field of word of memory
• EXG Exchange; Motorola 680x0, Motorola 68300; exchanges the data (32 bits) in two data registers; does not affect flags
• XCHG Exchange; Intel 80x86; exchanges the data (16 bits or 32 bits) in a register with the AX or EAX register or exchanges the data (8 bits, 16 bits, or 32 bits) in a register with the contents of an effective address (register or memory); LOCK prefix and LOCK# signal asserted in XCGHs involving memory; does not affect flags
• MOVSX Move with Sign Extension; Intel 80x86; moves data from a register or memory to a register, with a sign extension (conversion to larger binary integer: byte to word, byte to doubleword, or word to doubleword); does not affect flags
• MOVZX Move with Zero Extension; Intel 80x86; moves data from a register or memory to a register, with a zero extension (conversion to larger binary integer: byte to word, byte to doubleword, or word to doubleword); does not affect flags
• MOVZ Move Zero Extended; DEC VAX; moves an unsigned integer to a larger unsigned integer with zero extend, source and destination in register or memory (MOVZBW Byte to Word, MOVZBL Byte to Long, MOVZWL Word to Long); sets or clears flags
• MCOM Move Complemented; DEC VAX; moves the logical complement (one’s complement) of an integer to register or memory (MCOMB 8 bits, MCOMW 16 bits, or MCOML 32 bits); sets or clears flags
• LCR Load Complement from Register; IBM 360/370; RR format; fetches a full word (32 bits) of data from one of 16 general purpose registers, complements the data, and stores a full word (32 bits) of data in one of 16 general purpose registers; register to register only; sets or clears flags
• LPR Load Positive from Register (absolute value); IBM 360/370; RR format; fetches a full word (32 bits) of data from one of 16 general purpose registers, creates the absolute value (positive) the data, and stores a full word (32 bits) of data in one of 16 general purpose registers; register to register only; sets or clears flags
• MNEG Move Negated; DEC VAX; moves the arithmetic negative of a scalar quantity to register or memory (MNEGB 8 bits, MNEGW 16 bits, MNEGL 32 bits, MNEGQ 64 bits, MNEGF 32 bit float, or MNEGD 64 bit float); if source is positive zero, result is also positive zero; sets or clears flags
• LNR Load Negative from Register (negative of absolute value); IBM 360/370; RR format; fetches a full word (32 bits) of data from one of 16 general purpose registers, creates the absolute value the data, complements (negative) the absolute value of the data, and stores a full word (32 bits) of data in one of 16 general purpose registers; register to register only; sets or clears flags
• LDAN Load A-register Negative; MIX; move word or partial word field of data, load sign field with opposite sign; main storage to accumulator only
• LDXN Load X-register Negative; MIX; move word or partial word field of data, load sign field with opposite sign; main storage to extension register only
• LDiN Load index-register Negative; MIX; move word or partial word field of data, load sign field with opposite sign; main storage to one of five index registers only
• STZ Store Zero; MIX; move word or partial word field of data, store zero into designated word or field of word of memory
• MVC MoVe Character; IBM 360/370; SS format; moves one to 256 characters (8 bits each) of data; main storage to main storage only; does not affect condition code
• MOVE Move (block); MIX; move the number of words specified by the F field from location M to the location specified by the contents of index register 1, incrementing the index register on each word moved
• MOVEM Move Multiple; Motorola 680x0, Motorola 68300; move contents of a list of registers to memory or restore from memory to a list of registers; does not affect condition code
• LM Load Multiple; IBM 360/370; RS format; moves a series of full words (32 bits) of data from memory to a series of general purpose registers; main storage to register only; does not affect condition code
• STM STore Multiple; IBM 360/370; RS format; moves contents of a series of general purpose registers to a series of full words (32 bits) in memory; register to main storage only; does not affect condition code
• PUSHA Push All Registers; Intel 80x86; move contents all 16-bit general purpose registers to memory pointed to by stack pointer (in the order AX, CX, DX, BX, original SP, BP, SI, and DI ); does not affect flags
• PUSHAD Push All Registers; Intel 80386; move contents all 32-bit general purpose registers to memory pointed to by stack pointer (in the order EAX, ECX, EDX, EBX, original ESP, EBP, ESI, and EDI ); does not affect flags
• POPA Pop All Registers; Intel 80x86; move memory pointed to by stack pointer to all 16-bit general purpose registers (except for SP); does not affect flags
• POPAD Pop All Registers; Intel 80386; move memory pointed to by stack pointer to all 32-bit general purpose registers (except for ESP); does not affect flags
• STJ Store jump-register; MIX; move word or partial word field of data; jump register to main storage only
• MOVEP Move Peripheral Data; Motorola 680x0, Motorola 68300; moves data (16 bits or 32 bits) from a data register to memory mapped peripherals or moves data from memory mapped peripherals to a data register, skipping every other byte

About assembly language 68k family

www.shsu.edu/~csc_tjm/fall2002/cs333/module6a.pdf

Introduction of Assembly Language

 Language is a medium of communication between two or more individuals or parties.  The most important criteria in the communication is the message it brings must be effectively delivered, this is achieved only if the language is understood by the both parties.  What if the language is not compatible to both parties?  Then a translator is needed.  For instance, a Japanese requires a Japanese-Malays Translator to communicate to a Malaysian.

The most important task of the communication between computer and human is the message sent by programmers (program instructions) understood by the computer, and vise-verse.  Since human are so smart, they develop languages that are friendly to human and also understandable to computer systems.  In this unit, we will learn three basic programming languages known as machine language, assembler language and high level language.  The three languages has different levels of extreme between the machine (i.e. computer system) and human being (i.e. the programmers).

The nature of computer system is machine language level.  The assemble language is the developed version of a language to be more friendly to the programmers, and further developed to the high level language which gives the most friendly environment to the programmers.  Since the nature language of a computer system is machine language, we need translator assembler and compiler to convert the assembly language and high level language respectively into machine language.