Instruction and Description of M68000

Instruction	Descritption
ABCD ADD AND ASL ASR	Add Decimal with Extend Add Logical AND Arithmetic Shift Left Arithmetic Shift Right
B<cc> BCHG BCLR BRA BSET BSR BTST	Branch Conditionally Bit Test and Change Bit Test and Clear Branch Always Bit Test and Set Branch to Subroutine Bit Test
CHK CLR CMP	Check Reigster Against Bounds Clear Operand Compare
DB<cc> DIVS DIVU	Decrement and Branch Conditionally Signed Divide Unsigned Divide
EOR EXG EXT	Exclusive OR Exchange Registers Sign Extend
JMP JSR	Jump Jump to Subroutine
LEA LINK LSL LSR	Load Effective Address Link Stack Logical Shift Left Logical Shift Right
MOVE MULS MULU	Move Source to Destination Signed Multiply Unsigned Multiply
NBCD NEG NOP NOT	Negate Decimal with Extened Negate No Operation One's Complement
OR	Logical OR
PEA	Push effective Address
RESET ROL ROR ROXL ROXR RTD RTE RTR RTS	Reset External Devices Rotate Left without Extend Rotate Right without Extend Rotate Left with Extend Rotate Right wiht Extend Return and Delocate Return from Exception Return and Restore Return from Subroutine
SBCD S<cc> STOP SUB SWAP	Subtract Decimal wiht Extend Set Conditional Stop Subtract Swap data register halves
TAS TRAP TRAPV TST	Test and Set Operand Trap Trap on Overflow Test

Bit Manipulation

Bit manipulation instructions manipulate a specific bit of a bit string (or operand treated as a bit string). Bit clear changes the specified bit to zero. Bit set changes the specified bit to one. Bit change modifies a specified bit, clearing a one bit to zero and setting a zero bit to one. In some processors, the value of the bit before modification is tested. Bit test examines the value of a specified bit.

Bit scan instructions search a bit string for the first bit that is set or cleared (depending on the processor).

• BTST Bit Test; Motorola 680x0, Motorola 68300; tests the value of a specified bit in a register or memory location (8 bit memory operands, 32 bit register operands); sets or clears flags
• BIT Bit Test; Intel 80x86; tests the value of a specified bit in a general register or memory location; sets or clears flags
• BCLR Bit Test and Clear; Motorola 680x0, Motorola 68300; tests the value of a specified bit in a register or memory location (8 bit memory operands, 32 bit register operands), then clears the specified bit to zero; sets or clears flags
• BTR Bit Test and Reset; Intel 80x86; tests the value of a specified bit in a general register or memory location, then clears (resets) the specified bit to one; sets or clears flags
• BSET Bit Test and Set; Motorola 680x0, Motorola 68300; tests the value of a specified bit in a register or memory location (8 bit memory operands, 32 bit register operands), then sets the specified bit to one; sets or clears flags
• BTS Bit Test and Set; Intel 80x86; tests the value of a specified bit in a general register or memory location, then sets the specified bit to one; sets or clears flags
• BCHG Bit Test and Change; Motorola 680x0, Motorola 68300; tests the value of a specified bit in a register or memory location (8 bit memory operands, 32 bit register operands), then either clears a one bit to zero or sets a zero bit to one; sets or clears flags
• BTC Bit Test and Complement; Intel 80x86; tests the value of a specified bit in a general register or memory location, then complements; sets or clears flags
• BSF Bit Scan Forward; Intel 80x86; scans a word (16 bits) or doubleword (32 bits) in memory or a general register from low-order to high-order (starting from bit index zero) for a one-bit and store the index of the first set bit into a register (if no set bit is found, the value of the destination register is undefined); sets or clears flags
• BSR Bit Scan Reverse; Intel 80x86; scans a word (16 bits) or doubleword (32 bits) in memory or a general register from high-order to low-order (starting from bit index 15 of a word or index 31 of a doubleword) for a one-bit and store the index of the first set bit into a register (if no set bit is found, the value of the destination register is undefined); sets or clears flags

For example bit manipulation search this :

https://en.wikipedia.org/wiki/Bit_manipulation#Example_of_bit_manipulation

Binary Coded Decimal

  Binary coded decimal (BCD) is a method for implementing lossless decimal arithmetic (including decimal fractions) on a binary computer. The most obvious uses involve money amounts where round-off error from using binary approximations is unacceptable. Some early computers used BCD exclusively.

    Decimal digits (0-9) can be encoded in a nibble (half a byte), with some left over bit patterns (hexadecimal A-F). In BCD operations, the processor performs ordinary binary computations, then adjusts the result to conform to BCD. For example, if you add the binary number 5 (bit pattern 0101) to binary number 6 (bit pattern 0110), you get the binary result of 11 (bit pattern 1011, or hexadecimal B). With BCD arithmetic, the processor would adjust the result to make it into a valid BCD result (which in this case would be bit pattern 0001 0001).

    BCD arithmetic includes BCD addition, BCD subtraction, BCD multiplication, BCD division, and BCD negate.

    The Intel 80x86 series uses a two step approach for BCD arithmetic. Instead of having separate BCD instructions, the normal binary addition and subtraction instructions are used, then hardware instructions are used to adjust the results to correct BCD results. There are instuctions for both packed and unpacked adjustments. The advantage of this approach is greater flexibility (more addressing modes and choices of arithmetic operations because of the use of regular binary integer instructions in the first step). The disadvantage of this approach is that it is slower and takes more memory.

    Pack (Motorola 680x0) converts byte encoded numeric data (such as ASCII or EBCDIC characters) into binary coded decimals. Unpack (Motorola 680x0) converts binary coded decimals into byte encoded numeric data (such as ASCII or EBCDIC characters). The ASCII adjustment field is $3030; the EBCDIC adjustment field is $F0F0.

• ABCD Add Decimal with Extend; Motorola 680x0, Motorola 68300; performs binary coded decimal addition of source plus destination plus extend bit, source and destination can be two data registers or two locations in memory with the two address pointer registers being predecremented; sets or clears flags
• SBCD Subtract Decimal with Extend; Motorola 680x0; performs binary coded decimal subtraction of source and extend bit from destination, source and destination can be two data registers or two locations in memory with the two address pointer registers being predecremented; sets or clears flags
• NBCD Negate Decimal with Extend; Motorola 680x0, Motorola 68300; performs tens complement of contents of a data register or memory location by performing decimal coded binary subtraction of destination and extend bit from zero; sets or clears flags
• DAA Decimal Adjust after Addition; Intel 80x86; adjusts the result of adding two valid packed decimal operands in AL register; sets or clears flags
• DAS Decimal Adjust after Subtraction; Intel 80x86; adjusts the result of subtracting two valid packed decimal operands in AL register; sets or clears flags
• AAA ASCII Adjust after Addition; Intel 80x86; changes the contents of register AL to a valid unpacked decimal number, and zeros the top 4 bits; sets or clears flags
• AAS ASCII Adjust after Subtraction; Intel 80x86; changes the contents of register AL to a valid unpacked decimal number, and zeros the top 4 bits; sets or clears flags
• AAM ASCII Adjust after Multiplication; Intel 80x86; corrects the result of a multiplication of two valid unpacked decimal numbers, the high order digit is left in AH, the low order digit in AL; sets or clears flags
• AAD ASCII Adjust before Division; Intel 80x86; modifies the numerator in AH and AL to prepare for the division of two valid unpacked decimal operands so that the quotient produced by the division will be a valid unpacked decimal number, AH should contain the high-order digit and AL the low-order digit, this instruction adjusts the value and places the result in AL, AH will contain zero.; sets or clears flags
• PACK Pack; Motorola 680x0; converts converts byte encoded numeric data (such as ASCII or EBCDIC characters) into binary coded decimals using an adjustment field ($3030 for ASCII, $F0F0 for EBCDIC), either from data register to data register or memory location to memory location with predecrement of address pointers; does not modify flags
• UNPK Unpack; Motorola 680x0; converts converts converts binary coded decimals into byte encoded numeric data (such as ASCII or EBCDIC characters) using an adjustment field ($3030 for ASCII, $F0F0 for EBCDIC), either from data register to data register or memory location to memory location with predecrement of address pointers; does not modify flags

Shift and Rotate

 Shift instructions move a bit string (or operand treated as a bit string) to the right or left, with excess bits discarded (although one or more bits might be preserved in flags). In arithmetic shift left or logical shift left zeros are shifted into the low-order bit. In arithmetic shift right the sign bit (most significant bit) is shifted into the high-order bit. In logical shift right zeros are shifted into the high-order bit.

Rotate instructions are similar to shift instructions, ecept that rotate instructions are circular, with the bits shifted out one end returning on the other end. Rotates can be to the left or right. Rotates can also employ an extend bit for multi-precision rotates.

Shift Operations

·         The ALU used in the 6800 performs shift and rotate operations.  The ASL, ASR and LSR instructions are shown in Figure 3.15

Figure 3.15: 6800 Shift Instruction :  (a) Arithmetic Shift Left (ASL)

(b) Arithmetic Shift Right (ASR)   (c) Logical Shift Right (LSR)

·         In the ASL operation, the MSB is shifted out of the data word into the Carry bit.  The LSB is filled with a 0.

·         The ASR operations shifts each bit to the right and moves the LSB into the  Carry bit.  The MSB, however, is retained and is also shifted into bit 6.  If the bits in the register are considered as a 2’s complement number; this method of shifting preserves the sign of the number.  The ASR is equivalent to dividing the number in the register by 2, regardless of the sign of the number.

·         The LSR operation simply shifts each bit one position to the right.  The MSB becomes a 0 and the LSB goes into the Carry bit.

                        Rotations

·         Two additional shifting instructions are ROL (Rotate Left) and ROR (Rotate Right) shown in Figure 3.16.  These are special forms of circular shifting, where the bits coming off one end of the word are inserted into the Carry bit, whereas the contents of the Carry bit are transferred into the vacated bit position.

·         There are many uses for Rotate instructions.  One application is to determine parity of a byte.  If the bits of the byte are successively shifted into the Carry bit, the number of 1’s can be counted and the parity can be determined as an ODD or EVEN number. 

6800 Data Manipulation Instructions

·  Addition is done by insert one number to the accumulator and then added it with another number by using ADD instruction.

·   Memory content are added with content of accumulator and result of addition will store into accumulator.

·   This instruction have three (3) addressing mode which is immediate, direct and extended.

·   Arithmetic operation will change value of flag N, Z, V, and C.  By checking C bit in CCR after addition, borrow value can be check.  If borrow value produce by before operation, so C flag will be set.

·   6800 is a 8-bit microprocessor, so it can handle only 255 maximum number.  The bigger number can be handle by using more than one byte memory.  Value of two byte can be store until 65,535 and three byte can be store until 16,777,215.

·   Number with multiple byte is store in side-by-side position.

·   In arithmetic multiple byte, the operation start at the lower byte and the carry value will be used in the operation on the upper byte.

·   The operation of ADC (Add to accumulator with carry) instruction are same as ADD instruction operation.  The differences are carry bit from lower byte operation are add to the current addition process (or upper byte).  This instruction have three (3) addressing mode which is immediate, direct and extended.

·   Subtraction operation have been done by using SUB (subtract from accumulator) and SBC (subtract from accumulator with carry).  SUB Instruction operation are not involve Carry flag.  SBC instruction will subtract 1 from result if C flag are set 1, if not their effect are same as SUB instruction operation.

·   The value in accumulator A can be added with value in accumulator B and their result store at accumulator A by using ABA (Add ACCB to ACCA) instruction also value in accumulator A can be subtract from accumulator B by using SBA (subtract ACCB from ACCA) instruction.

·   Another arithmetic instruction are NEG (Negate), CLR (Clear), INC (Increment) and DEC (Decrement).  NEG instruction are using for get the 2 complement’s operand.  CLR instruction are used to put zero value to the destination of the operand.  INC instruction are used to added 1 to the operand to get the address of the operation where else DEC instruction are used to subtract 1 from the operand. 

Integer Arithmetic

 The basic four integer arithmetic operations are addition, subtraction, multiplication, and division. Arithmetic operations can be signed or unsigned (unsigned is useful for effective address computations). Some older processors don’t include hardware multiplication and division. Some processors don’t include actual multiplication or division hardware, instead looking up the answer in a massive table of results embedded in the processor.

 A specialised, but common, form of addition is an increment instruction, which adds one to the contents of a register or memory location. For address computations, “increment” may mean the addition of a constant other than one. Some processors have “short” or “quick” addition instructions that extend increment to include a small range of positive values.

 A specialised, but common, form of subtraction is an decrement instruction, which subtracts one from the contents of a register or memory location. For address computations, “decrement” may mean the subtraction of a constant other than one. Some processors have “short” or “quick” subtraction instructions that extend decrement to include a small range of values.

 Compare instructions are used to examine one or more integers non-destructively. These are usually implemented by performing a subtraction in some shadow register or accumulator and then setting flags accordingly. Compare instructions can compare two integers, or can compare a single integer to zero. Triadic compare instructions compare a test value to an upper and lower limit, which can be useful for bounds and range checking.

Some processors have specific hardware support for large multi-byte integer arithmetic. Even if there is no specific support, generally carry and borrow flags can be used to implement software multi-byte arithmetic routines.

  Some processors have other special integer arithmetic operations. A clear instruction sets a register or memory location to zero. Some processors have special instructions for setting a register to a special value (such as pi) with additional guard bits also being set appropriately. A sign extend operation takes a small value and sign extends it to a larger storage format (such as byte to word). An arithmetic complement gives the arithmetic complement of a number (one’s complement). An arithmetic negate gives the arithmetic inverse of a number (subtract from zero; two’s complement).

Diagram